1. Technical Field
This invention relates to the area of digital data communications and in particular, to the communication of digital data through high speed interconnects between devices characterized by data block sizes larger than the burst transfer size supported by the interconnect.
2. Background Art
High performance buses and bus-like interconnects ("interconnects") are characterized by relatively small block transfer sizes and correspondingly short arbitration latencies. For example, the Scalable Coherent Interconnect (SCI, IEEE Std 1596-1992) provides bus-like read and write transactions of sixty four (64) bytes each, as does Serial Express, a proposed higher-performance, longer-distance extension of the Serial Bus (IEEE Std. 1394-1995). Both interconnects are designed to support high-speed data transfers between high speed devices such as video cameras/monitors, PCI-card chassis, high performance I/O devices, and Serial Bus bridges.
The relatively small burst transfer size supported by SCI and Serial Express can create a bottleneck when data packets are being transported between devices that support larger sized data blocks, i.e. much larger than 64 bytes. A general rule of thumb for efficient data transfer across a bus is that the time necessary for arbitration and header transmission should allow on the order of 75% of the time to be available for transferring data. Thus, buses with longer arbitration latencies (such as Serial Bus) typically support large data block transfers. If a data block is simply fragmented into multiple 64-byte data packets for transmission through an intermediate Serial Express interconnect, subsequent transmission of each fragmented data packet on the remote Serial Bus would be inefficient. In effect, each data burst would be subject to the longer arbitration latency of the remote Serial Bus, making transfer of the data on the remote Serial Bus very slow.
The mismatch in block sizes and the resulting bottleneck may be substantial as, for example, where a pair of Serial Buses are coupled by a Serial Express interconnect through a pair of Serial Express-Serial Bus bridges. In this case, a 4k byte burst transfer originating on one Serial Bus is fragmented at the first bridge into sixty four 64-byte burst transfers for transmission through the interconnect. If treated independently, each of the sixty four 64-byte burst transfers will be subject to the Serial Bus arbitration latency at the second bridge.
Another problem presented by the mismatch in burst transfer sizes occurs where a bus master on a PCI bus writes data to a memory on a host bus through a Serial Express interconnect. Given the relatively high latency for host bus memory accesses, the Serial Express-to-PCI bridge requires a large posted write buffer for efficient data transfer. Simply fragmenting a large, contiguous block of posted writes into 64-byte burst transfers for concurrent transmission across the interconnect will not work correctly. Posted-writes must be delivered in the order received, but high performance interconnects like Serial Express (and SCI) can re-order the 64-byte blocks during transmission.
Mismatches in data block sizes can also create inefficiencies where devices other than buses are coupled through high speed interconnects. For example, large data blocks may be written from a hard disc to memory through a high speed interconnect. Address translation for such writes will be more efficient if memory processes the data as a block rather than as multiple fragments.
In each case described, the transmission inefficiencies arise because there is no effective block transfer protocol to recognize the integrity of the original data block and reconstruct the data block following transmission through the interconnect. PCI bus protocols include hint bits, which may be used to indicate when additional read or write transactions should be expected. However, the hint bits do not specify the amount of additional data. Nor do the hint bits or any other elements of the PCI bus protocol provide means for committing resources to the transaction or reassembling fragmented data blocks following transmission. Likewise, the inclusion of future-use hints in transactions are of marginal utility because the interconnect may reorder the original transaction, which includes the future use hint, with respect to the following transactions to which the hint applies.
There is thus a need for a system and method for maintaining the integrity of large data blocks when they are fragmented for transfer through a high speed interconnect, supporting burst transfer sizes that are smaller than the data block.